1. Field
This disclosure relates generally to integrated circuit design, and more specifically to the placement of gate array circuits in an integrated circuit design.
2. Description of the Related Art
Logic synthesis is a computer implemented process that transforms a circuit description from one level of abstraction to a lower level, usually towards the physical implementation of an integrated circuit. As a result of the logic synthesis process, logic cells or logic functions are arranged physically on an integrated circuit chip in multiple circuit rows and/or circuit columns in order to form the completed design. Each circuit row and/or circuit column on the integrated circuit chip contains multiple logic cells that are arranged adjacent to one another.
After the logic cells are positioned in the integrated circuit chip design, gaps or empty spaces are likely to remain between certain adjacent logic cells. These empty spaces, sometimes referred to as “white spaces”, exist in random locations and are of random sizes within the circuit design layout.
Filler cells may be established within the empty white spaces. Filler cells are functional cells that are added to the integrated circuit design layout to fill the empty spaces between the logic cells within the circuit rows and/or circuit columns of the original circuit design, or nonfunctional cells that only contain shapes to maintain uniformity during manufacturing. A functional filler cell may include, for example, one or more passive electronic devices, such as resistors or decoupling capacitors, or one or more active electronic devices, such as standard logic gates. The size of the physical area of the filler cell determines the scope of functionality that may be incorporated therein. For example, a filler cell of a certain size may allow only for the incorporation of a nonfunctional cell. By contrast, a filler cell of a certain larger size may allow the incorporation of a more complex logic function, such as a gate array fill circuit.
Gate array fill circuits, in the context of integrated circuit design, are customizable devices that are formed of transistors. Gate array fill circuits are formed as configurations of electrical substrate, diffusion layer, and gate layer formed in a regular pattern on a semiconductor chip. Gate array fill circuits are configurable into gate array logic elements by “back end of line” process steps that are performed late in the integrated circuit manufacturing process, such as metal and metal-to-metal cut layer deposition. Such customizable gate array fill circuits are very useful to have available as part of an integrated circuit chip design.
The fabrication of an integrated circuit chip is a complex process that involves multiple steps of diffusion into and deposition onto a semiconductor substrate to form multiple physical layers. Each layer of the integrated circuit chip is defined by a unique mask that is used during the fabrication process. The pattern defined by each mask is derived from the logic synthesis process described above in order to translate the layout of logic cells and filler cells defined by an integrated circuit design into physical structures at multiple layers of the semiconductor chip to implement the desired circuit functionality. Each such mask used in an integrated circuit manufacturing process is very complicated and expensive to produce.
A problem with an integrated circuit design, such as a functional problem or a circuit timing problem with a logic cell, may be discovered after integrated circuit manufacturing processes, such as mask fabrication or even semiconductor processing, have been begun, or even have been completed. The requirement for a design change late in the integrated circuit fabrication process is almost unavoidable, due to the complexity of integrated circuit designs in combination with increasingly tight time-to-market requirements for new designs. A design change to the logic cells at this point might require scrapping masks or even processed semiconductor substrates and could be very expensive. However, the availability of customizable gate array fill circuits as part of the chip design provides the circuit designer the opportunity to implement circuit modifications that may be required in a much more cost effective way. Gate array fill circuits may be configured into fully configured gate array logic elements to implement the desired functionality changes to the integrated circuit. Since the gate array logic elements may be formed from available gate array fill circuits via a backend release to the manufacturing process, such changes may be implemented with minimum disruption to an established manufacturing process. Furthermore, multiple changes to an integrated circuit design may be supported in this cost effective manner. As additional problems with an integrated circuit design may be discovered, available gate array fill circuits may be configured and reconfigured as necessary to implement the desired design changes.
Since gate array fills circuits can prove so valuable, it is desirable that the number and size of gate array fill circuits that are available to circuit designers on an integrated circuit chip be maximized. A particular challenge is to maximize the gate array fill circuits that remain available for configuration even as other gate array fill circuits are configured into gate array logic elements to implement needed circuit design changes. Maximizing gate array fill circuit density in an efficient manner is constrained by the limitations of current integrated circuit manufacturing processes and limited by currently available methods for positioning of configurable gate array fill circuits and fully configured gate array logic elements in an integrated circuit design.
Modern integrated circuit technology manufacturing constraints impose minimum distances between gate conductor layer materials and minimum distances between metal or metal-to-metal cut layer materials forming gate interconnects that may differ from one another. For purposes of enabling automated routing tools, circuit library elements are often designed to be aligned in step sizes of the metal pitch, for example, while circuit performance dictates that gate devices are placed as closely together as possible. Thus, gate array fill circuits are usually designed in multiples of the least common multiple of the placement/wiring step size and the gate layer pitch. This enables abutment of gate array fill circuits in a continuous pattern of substrate, diffusion (well), and gate devices that is advantageous both to decreasing variability in the manufacturing process and to supporting configuration of gate array logical elements that can be even larger than one individual gate array fill circuit.
Currently, the positioning of gate array logic elements in an integrated circuit design that contains previously positioned logic cells, with gate array fill circuits positioned between adjacent logic cells, may be performed either manually or with an automated placement tool. For example, a circuit designer might replace manually one or more gate array fill circuits in an integrated circuit design with one or more gate array logic elements. Of course, such a manual approach is time consuming. Furthermore, maximizing gate array fill circuit availability in the integrated circuit design with manual gate array logic element and gate array fill circuit positioning is heavily dependent upon the skill of the designer.
Current automated placement tools impose a restriction of the sites on the integrated circuit chip at which a fully configured gate array logic element might be placed to that least common multiple step size of the placement grid and the gate layer pitch. Thus, such a tool will automatically position a logic element in the integrated circuit design in alignment with a least common multiple step size grid that is defined across the entire integrated circuit design area. This approach is general, in that it enforces the same pattern across separate rows or columns of circuit placement, conducting wells, substrate areas, and the like.